Integrated circuits, such as display drivers, use control voltages of up to 100 volts while being controlled by standard 5-volt CMOS logic circuits. Thus, complex voltage level shifting devices are needed to convert a 5-V signal into an output signal with the desired level. As such devices are commonly integrated into battery-powered apparatuses, they must have the lowest possible power consumption.
Cholesteric liquid crystal screens have been developed and are used in particular in apparatuses having a very low image modification frequency. Such screens are used for their capacity to store the image in the absence of a power supply, but require the application of voltages on the order of 50 to 100 volts over their pixel lines in order for the image to be modified. Such screens thus require display drivers supplying such voltages with an extremely low power consumption.
A known display driver has three voltage sources having different levels that must be selectively applied to a pixel by an output node Vout. A first source supplies a high voltage, a second source supplies an intermediate voltage, and a third source supplies a low voltage. The second voltage source includes a so-called static voltage shifting device. Such a voltage shifting device converts a low-voltage signal for controlling an analog switch equipped with high-voltage PMOS transistors T1 and T2 mounted head-to-tail as shown in FIG. 1. This head-to-tail assembly makes it possible to switch from the high voltage to the intermediate voltage without returning to the low voltage. The transistors T1 and T2 also form two parasitic diodes D1 and D2 arranged head-to-tail. The drain of transistor T2 is coupled to a high-voltage power supply Hv and the drain of transistor T1 is coupled to the output node Vout. The sources of transistors T1 and T2 are coupled to one another. The output voltage on the node Vout is determined by the difference in voltage between the source of T4 and the drain of T3. This voltage difference is generated by the current supplied by a current source Ibias and passing through diode-connected transistors T3 and T4.
The disadvantage of such a voltage level shifting device is that the current source Ibias continuously consumes power. Such a continuous power consumption is unacceptable for a battery power supply.
FIG. 2 shows a so-called dynamic voltage level shifting device controlling an analog switch equipped with high voltage PMOS transistors T1 and T2. This device is also described in A New Architecture for Monolithic Low-Power High-Voltage Display Driver by Doutreloigne, De Smet and Van Calster of the University of Gant (ISSN1083-1312/00/2001-0115). This device uses a dynamic gate charge control for transistors T1 and T2 so as to suppress the static consumption of the voltage level shifting device of FIG. 1.
The sources of transistors T1 and T2 are coupled to one another. The gates of transistors T1 and T2 are coupled to one another. The drain of T2 is coupled to a high voltage power supply Hv and the drain of transistor T1 is coupled to an output node Vout. Transistors T1 and T2 also form two parasitic diodes D1 and D2.
The voltage level shifting device includes a capacitor C coupled between the source and the gate of transistors T1 and T2. The voltage level shifting device also includes standard CMOS transistors T4 to T9 for charging and discharging the capacitor C.
Transistors T5 and T7 are used for charging the capacitor C and are coupled in series between the source of transistor T1 and the ground. Transistor T5 is an NMOS power transistor receiving a charge control signal on its gate. The anode and cathode of a diode D3 are coupled respectively to the gate of T1 and to the drain of T5. Transistor T7 is a PMOS transistor having a connection between its gate and its drain.
Transistors T4, T6 and T8 are used to discharge the capacitor C. Transistors T4 and T6 are coupled in series between the source of transistor T1 and the ground. Transistor T4 is an NMOS power transistor receiving a discharge control signal on its gate. Transistor T6 is a PMOS transistor having a connection between its gate and its drain. The source of transistor T8 is coupled to the source of T1, its drain is coupled to the gate of T1 and its gate is coupled to the gate of T6.
The charge and discharge signals applied respectively to T5 and T4 have a very low cyclic ratio, so as to minimize the consumption of the voltage level shifting device.
Such a voltage level shifting device has disadvantages, however. Cyclic charge and discharge signals are necessary. In addition, the substrate surface occupied by such a device is large.
Moreover, transistors T1 and T2 are sensitive to the voltage level on the output node Vout. Thus, if another circuit applies a voltage Vout over the level Hv, a current passes through diode D1 and the capacitor C and charges the parasitic capacitances between the ground and the gate of T1. The charge of the capacitor C, of which the capacitance is limited so as to facilitate its integration, then causes transistors T1 and T2 to be turned on. Thus, the analog switch generates a parasitic consumption and the voltage on the node Vout decreases with respect to its nominal level.